Calibration for mixed-signal integrator architecture

ABSTRACT

A mixed signal correlator utilizes coherent detection within a capacitance measurement application. In some applications, the mixed signal correlator is used to measure capacitance of a touch screen display. An external capacitor whose capacitance is measured is kept small for improved sensitivity and can be used for a variety of applications having varied integration periods for measurement. The external capacitor is kept small and can be used for varied applications by adjusting the output voltage within a range that is less than the supply voltage, and maintaining a count of the adjustments to later reconstruct an actual output voltage for the integration period. An output is a weighted sum of an analog integrator output and a digital counter output.

RELATED APPLICATIONS

This application claims priority of U.S. provisional application Ser.No. 61/446,944, filed Feb. 25, 2011, and entitled “Mutual CapacitanceTouch-Screen Controller IIC Interface”, by these same inventors. Thisapplication incorporates U.S. provisional application Ser. No.61/446,944 in its entirety by reference.

FIELD OF THE INVENTION

This invention relates to analog front end circuits for convertingmeasured capacitances to voltages. More specifically, this inventionrelates to analog front end circuits having a mixed-signal correlator ora mixed-signal integrator for demodulating a measured capacitance froman excitation signal.

BACKGROUND OF THE INVENTION

Many electrical devices are incorporating touchscreen type displays. Atouchscreen is a display that detects the presence, location, andpressure of a touch within the display area, generally by a finger,hand, stylus, or other pointing device. The touchscreen enables a userto interact with the display panel directly without requiring anyintermediate device, rather than indirectly with a mouse or touchpad.Touchscreens can be implemented in computers or as terminals to accessnetworks. Touchscreens are commonly found in point-of-sale systems,automated teller machines (ATMs), mobile phones, personal digitalassistants (PDAs), portable game consoles, satellite navigation devices,and information appliances.

There are a number of types of touchscreen technologies. A resistivetouchscreen panel is composed of several layers including two thinmetallic electrically conductive and resistive layers separated by thinspace. When some object touches the touchscreen panel, the layers areconnected at certain point. In response to the object contact, the panelelectrically acts similar to two voltage dividers with connectedoutputs. This causes a change in the electrical current that isregistered as a touch event and sent to the controller for processing.

A capacitive touchscreen panel is coated, partially coated, or patternedwith a material that conducts a continuous electrical current across asensor. The sensor exhibits a precisely controlled field of storedelectrons in both the horizontal and vertical axes to achievecapacitance. The human body is conductive; therefore, influenceselectric fields stored in a capacitance. When a reference capacitance ofthe sensor is altered by another capacitance field, such as a finger,electronic circuits located at each corner of the panel measure theresultant distortion in the reference capacitance. The measuredinformation related to the touch event is sent to the controller formathematical processing. Capacitive sensors can either be touched with abare finger or with a conductive device being held by a bare hand.Capacitive sensors also work based on proximity, and do not have to bedirectly touched to be triggered. In most cases, direct contact to aconductive metal surface does not occur and the conductive sensor isseparated from the user's body by an insulating glass or plastic layer.Devices with capacitive buttons intended to be touched by a finger canoften be triggered by quickly waving the palm of the hand close to thesurface without touching.

FIG. 1 illustrates an exemplary conventional capacitive touch sensorused in a capacitive touchscreen panel. Such sensors are typicallyformed using transparent conductors, such as ITO (Indium Tin Oxide)conductors, formed in layers. In the exemplary configuration of FIG. 1,bottom conductors form drive electrodes X0, X1, X2, X3, also referred toas drive lines, and top conductors form sense electrodes Y0, Y1, Y2, Y3,also referred to as sense lines. Each cross-point of a drive line and asense line forms a capacitor having a measured capacitance Cm. Theobjective is to determine an estimate of a touch position on thecapacitive touch sensor. When a finger, or other object that isgrounded, is positioned on or proximate a cross-point of the sensor,there is a change in the measured capacitance Cm at that cross-point.The measured capacitance Cm is the capacitance between the sense lineand the drive line at the cross-point. When the touch event occurs atthe cross-point, a portion of the field lines between the sense line andthe drive line are diverted to between the sense line and the finger. Assuch the measured capacitance Cm decreases during a touch event.

An analog front end (AFE) circuit performs signal processing on ananalog signal and typically performs an analog-to-digital conversion.Analog front end circuits can be used in a variety of applications,including measuring and converting a capacitance to a correspondingvoltage. FIGS. 2A and 2B illustrate a simplified schematic block diagramof a conventional analog front end circuit used for measuring acapacitance of an external capacitor and converting the measuredcapacitance to a corresponding voltage. In an exemplary application, theexternal capacitance is the charge stored in the capacitor Cm of FIG. 1.FIG. 2A illustrates the circuit in a first phase, and FIG. 2Billustrates the circuit in a second phase. During phase 1, charge to bemeasured is collected on the capacitor Cm. During phase 2, the chargestored on the capacitor Cm is transferred to the capacitor Cf and acorresponding voltage Vout is output.

Referring to FIG. 2A, the circuit includes the capacitor Cm, anoperational amplifier 2, a switch 4, a feedback capacitor Cf, and aswitch 6. A voltage at the negative input of the amplifier 2, andtherefore at a first terminal of the capacitor Cm, is a virtual ground,Vvg. During phase 1, the switch 4 is connected to the reference voltageVref, and the switch 6 is closed. Closing the switch 6 enables thecapacitor Cf to completely discharge to a known zero state. The chargeacross the capacitor Cm is Vvg−Vref times the capacitance Cm.

During phase 2, the switch 4 is connected to ground, and the switch 6 isopened, as shown in FIG. 2B. With the switch 4 connected to ground thevoltage across the capacitor Cm is zero, and all the charge on thecapacitor Cm is transferred to the capacitor Cf. The output voltage Voutis a signal with amplitude dependent on the charge stored on thecapacitor Cm and transferred to the capacitor Cf. The output voltageVout can be input to an analog-to-digital converter (ADC), such as inFIG. 4, to be converted to a corresponding digital output value. Sincethe capacitor Cf was completely discharged during phase 1, the chargestored on capacitor Cf is determined entirely by the amount of chargetransferred from the capacitor Cm. If the capacitor Cf is not completelydischarged to a zero state during phase 1, then the capacitor Cf willretain the memory of its previous state.

The output voltage Vout=Vref*Cm/Cf+vn, where Vref is a known internalreference value, vn is the undesired noise measured by the system, andCf is a known value. As such, the capacitance Cm can be determined fromthe known values Vref and Cf and the measured value Vout. Thecapacitance Cm is a varying capacitance and represents the capacitanceto be measured, such as the measured capacitance of a touch screendisplay. As a finger touches the touch screen display, the capacitancechanges, which is the external capacitance change being measured.

A problem with the circuit of FIGS. 2A and 2B relates to wide-band noisesampling. The circuit does not include any noise filtering, so any noiseintroduced into the system at the transition from phase 1 to phase 2 isincluded within the charge transferred to the capacitor Cf. This noiseis represented as the component “vn” in the output voltage Vout. So notonly is the output voltage Vout a measure of the capacitance Cm, butalso an instantaneous sampling of the noise. Further, the dynamic rangeof the ADC needs to be large enough to account for the increasedmagnitude of the output voltage Vout due to noise. The larger dynamicrange results in an ADC that has a larger area and uses more power.

FIG. 3 illustrates exemplary response curves for the circuit of FIGS. 2Aand 2B. The top curve shows a sampling clock corresponding to phase 1and phase 2. When the sample clock is high, e.g. 1V, the circuit is inphase 1 (FIG. 1), and when the sample clock is low, e.g. 0V, the circuitis in phase 2 (FIG. 2). In an exemplary application, the input issampled on the rising edge of the sampling clock. The moment that theswitches 4 and 6 are changed from phase 2 to phase 1 the voltage Vout issampled. As shown in the middle curve of FIG. 3, there is some noise onthe input signal, but its average value is substantially constant. Thesampled value is expected to be constant, such as 1V, but due to thenoise the actual sampled output varies about the expected constant valuedepending on the instantaneous noise present at the sampling time. Anexample of this variation on the actual sampled output is shown in thebottom curve of FIG. 3. If the instantaneous noise is high, then theactual sampled output is greater than the expected constant value, suchas the portions of the sampled output curve that are above 1V. If theinstantaneous noise is low, then the actual sampled output is lower thanthe expected constant value, such as the portions of the sampled outputcurve that are below 1V.

In application, a threshold voltage for determining a change incapacitance, such as a touch event on a touch screen display, isincreased to accommodate the variation in the sampled output. Increasingthe threshold voltage reduces the sensitivity of the system. Using athreshold voltage that is too low to account for the noise variationsresults in false triggers.

Various alternative systems that measure a capacitance includeconsiderations for the noise. FIG. 4 illustrates a simplified schematicblock diagram of a conventional analog front end circuit using digitalfiltering. The circuit of FIG. 4 includes an analog-to-digital converter(ADC) connected to the output of the low-noise amplifier (LNA). Voltageinput to the ADC is converted to a digital value, which is processed bydigital processing circuitry that includes noise filtering. The ADC isalso a sampling system which samples at a single instant in time. Thisresults in similar varying sampled output values as described above inrelation to FIG. 3.

FIG. 5 illustrates a simplified schematic block diagram of anotherconventional analog front end circuit. The circuit of FIG. 5 is the sameas the circuit of FIG. 4 with the addition of a band-pass filter (BPF)to filter the signal prior to inputting to the ADC. The BPF attempts tofilter the noise present in the voltage signal (middle curve of FIG. 3)prior to inputting to the ADC. Sampling is performed on the filteredsignal output from the BPF. The problem with the circuit of FIG. 5 isthat different applications are subjected to different noise spectrums.As such, the BPF cannot be fixed, instead the BPF must be tunable to thespecific application. Also, the BPF should be able to be finely tuned toaccommodate applications with a relatively narrow frequency response.For example, a touch screen display may have a frequency responsebetween about 50-400 kHz. If the BPF has too large a bandwidth, such as50 kHz, the filter bandwidth may be too wide to effectively filter noisefor certain applications.

SUMMARY OF THE INVENTION

A mixed signal correlator utilizes coherent detection within acapacitance measurement application. In some applications, the mixedsignal correlator is used to measure an external capacitance, such asthat of a touch screen display. The correlator capacitance is kept smallfor improved sensitivity and can be used for a variety of applicationshaving varied integration periods for measurement. The correlatorcapacitance is kept small and can be used for varied applications byadjusting the output voltage within a range that is less than the supplyvoltage, and maintaining a count of the adjustments to later reconstructan actual output voltage for the integration period. An output is aweighted sum of an analog integrator output and a digital counteroutput. The actual output voltage is reconstructed using a digitizedvalue used for each voltage adjustment. The voltage adjustment value isa function of the capacitor ratio between an integrating feedbackcapacitor of the integrator and a dump capacitor of a voltage adjustmentcircuit. The actual value of the capacitor ratio can be measured using acalibration process.

In an aspect, an integration circuit is disclosed. The integrationcircuit includes an input control switch, an integrator, a voltageadjustment circuit, and a logic circuit. The input control switch isconfigured to switch to a first position coupled to an input voltagesignal and to a second position coupled to ground. The integrator iscoupled to an output of the input control switch, wherein the integratoris configured to output an integrated output voltage. A voltageadjustment circuit is coupled to the integrator, wherein the voltageadjustment circuit is configured to adjust the integrated output voltageby a voltage adjustment. The logic circuit is coupled to the voltageadjustment circuit and to the input control switch. The logic circuit isconfigured to control the voltage adjustment circuit and the inputcontrol switch. When the input control switch is set to the firstposition, the integrator integrates the input voltage signal and thevoltage adjustment circuit adjusts the integrated output voltage by thevoltage adjustment if the integrated output voltage reaches one or moredefined limits. When the input control switch is set to the secondposition, the integrator, the voltage adjustment circuit, and the logiccircuit are configured to perform a calibration process that measures avalue of the adjustment value.

The integration circuit can also include a resistive element coupled tothe output of the input control switch; an amplifier coupled to anoutput of the resistive element; and an integrating feedback capacitorcoupled to an input of the amplifier and to an output of the amplifier.The voltage adjustment circuit can include a charge dump capacitor,wherein the value of the voltage adjustment is set by a capacitanceratio of the charge dump capacitor and the integrating feedbackcapacitor. The voltage adjustment circuit can also include a pluralityof switches, wherein the charge dump capacitor is coupled to theintegrating feedback capacitor via a first switch of the plurality ofswitches, and the plurality of switches are coupled to the logiccircuit. The integration circuit can also include an analog-to-digitalconvertor coupled to the output of the integrator to convert theintegrated output voltage to a digital value at each integration timeperiod. The logic circuit can be configured to perform the calibrationprocess by measuring the digital value output from the analog-to-digitalconverter while the input control switch is in the second position,forcing the voltage adjustment circuit to adjust the integrated outputvoltage by the voltage adjustment while the input control switch is inthe second position, and measuring the digital value output from theanalog-to-digital converter after the forced voltage adjustment whilethe switch is in the second position. The voltage adjustment value canbe a fixed value Vj. The integration circuit can also include acomparison circuit coupled to the integrator, wherein the comparisoncircuit is configured to receive the integrated output voltage, tocompare the integrated output voltage to the one or more defined limits,and to output a comparison result to the logic circuit. The logiccircuit can include program instructions configured to perform the stepsof comparing the integrated output voltage to the one or more definedlimits, and to control the voltage adjustment circuit according to acomparison result. The resistive element can have a fixed impedance, orthe resistive element can have a time-varying impedance.

In another aspect, a method of calibrating an integration circuit isdisclosed. The method includes coupling an input of an integrator toground and discharging an integrating feedback capacitor within theintegrator, wherein an output of the integrating feedback capacitoroutputs an integrated output voltage according to a current chargeaccumulated by the integrating feedback capacitor. The method alsoincludes measuring the integrated output voltage to determine a firstcalibration voltage, and applying a charge dump to the integratingfeedback capacitor thereby adjusting the integrated output voltage. Themethod also includes measuring the integrated output voltage afterapplication of the charge dump to determine a second calibrationvoltage. The method also includes calculating a difference between thefirst calibration voltage and the second calibration voltage todetermine a measured adjustment voltage value that corresponds to thecharge dump. The method also includes discharging the integratingfeedback capacitor.

Calculating the difference between the first calibration voltage and thesecond calibration voltage can include converting the first calibrationvoltage to a first digital value, converting the second calibrationvoltage to a second digital value, and calculating a difference betweenthe first digital value and the second digital value. The method canalso include coupling the input of the integrator to receive an inputvoltage signal; comparing the integrated output voltage to one or morethreshold values to determine if the integrated output voltage is withina voltage range; adjusting the charge on the integrating feedbackcapacitor by applying the charge dump if the integrated output voltageis not within the voltage range, thereby maintaining the integratedoutput voltage within a voltage range; determining an accumulatedvoltage change corresponding to a number of adjustments in chargeapplied within an integrating period multiplied by the measuredadjustment voltage value; and determining a total integration voltageover the integrating period by adding the accumulated voltage change tothe integrated output voltage at the end of the integrating period.

Adjusting the charge can include decreasing the charge on the capacitorif the integrated output voltage is greater than or equal to a highthreshold value, and increasing the charge on the capacitor if theintegrated output voltage is less than or equal to a low thresholdvoltage, wherein decreasing the charge on the capacitor decreases theintegrated output voltage and increasing the charge on the capacitorincreases the integrated output voltage. Comparing the integrated outputvoltage to one or more threshold values can be performed in software orperformed using one or more comparators. Adjusting the charge on thecapacitor can result in adjusting the instantaneous integrated outputvoltage. Determining the total integration voltage can includeconverting the integrated output voltage to a digital value at eachintegration time period and adding the accumulated voltage change to thedigital value. The measured adjustment voltage value can include a fixedvalue.

BRIEF DESCRIPTION OF THE DRAWINGS

Several example embodiments are described with reference to thedrawings, wherein like components are provided with like referencenumerals. The example embodiments are intended to illustrate, but not tolimit, the invention. The drawings include the following figures:

FIG. 1 illustrates an exemplary conventional capacitive touch sensorused in a capacitive touchscreen panel.

FIGS. 2A and 2B illustrate a simplified schematic block diagram of aconventional analog front end circuit used for measuring a capacitanceof an external capacitor and converting the measured capacitance to acorresponding voltage.

FIG. 3 illustrates exemplary response curves for the circuit of FIGS. 2Aand 2B.

FIG. 4 illustrates a simplified schematic block diagram of aconventional analog front end circuit using digital filtering.

FIG. 5 illustrates a simplified schematic block diagram of anotherconventional analog front end circuit.

FIG. 6 illustrates a simplified schematic block diagram of an analogfront end circuit using coherent detection according to a firstembodiment.

FIG. 7 illustrates an exemplary frequency response of the circuit ofFIG. 6 for an excitation frequency f equal to 300 kHz.

FIG. 8 illustrates a schematic circuit diagram of an exemplary mixingcircuit according to an embodiment.

FIG. 9 illustrates a simplified schematic block diagram of an analogfront end circuit using coherent detection according to a secondembodiment.

FIG. 10 illustrates a schematic diagram of an integrated mixing andintegrating circuit including a transconductor as the time-varyingimpedance element according to an embodiment.

FIG. 11 illustrates a schematic diagram of an integrated mixing andintegrating circuit including a current digital to analog converter(IDAC) as the time-varying impedance element according to an embodiment.

FIG. 12 illustrates a schematic diagram of an integrated mixing andintegrating circuit including a programmable capacitive element as thetime-varying impedance element according to an embodiment.

FIG. 13 illustrates an output voltage Vout versus time curve for thecorrelator of FIG. 9, under the simplified conditions where theresistance R(t) and the input voltage V(t) are constant.

FIG. 14 illustrates a simplified schematic block diagram of a mixedsignal correlator according to an embodiment.

FIG. 15 illustrates an exemplary timing diagram corresponding tooperation of the mixed signal correlator of FIG. 14.

FIG. 16 illustrates a circuit for implementing the mixed signalcorrelator of FIG. 9 according to an embodiment.

FIG. 17 illustrates a simplified schematic block diagram of a mixedsignal correlator configured to perform a calibration process accordingto an embodiment.

FIG. 18 illustrates a voltage output Vout versus time curve for thefirst step of the calibration process.

FIG. 19 illustrates a voltage output Vout versus time curve for thesecond step of the calibration process.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Embodiments of the present application are directed to a mixed signalcorrelator. Those of ordinary skill in the art will realize that thefollowing detailed description of the mixed signal correlator isillustrative only and is not intended to be in any way limiting. Otherembodiments of the mixed signal correlator will readily suggestthemselves to such skilled persons having the benefit of thisdisclosure.

Reference will now be made in detail to implementations of the mixedsignal correlator as illustrated in the accompanying drawings. The samereference indicators will be used throughout the drawings and thefollowing detailed description to refer to the same or like parts. Inthe interest of clarity, not all of the routine features of theimplementations described herein are shown and described. It will, ofcourse, be appreciated that in the development of any such actualimplementation, numerous implementation-specific decisions must be madein order to achieve the developer's specific goals, such as compliancewith application and business related constraints, and that thesespecific goals will vary from one implementation to another and from onedeveloper to another. Moreover, it will be appreciated that such adevelopment effort might be complex and time-consuming, but wouldnevertheless be a routine undertaking of engineering for those ofordinary skill in the art having the benefit of this disclosure.

In some embodiments, a capacitance measurement is performed by an analogfront end circuit that uses coherent detection, also referred to assynchronous demodulation or correlation, to reject noise and/or otherinterferers. FIG. 6 illustrates a simplified schematic block diagram ofan analog front end circuit using coherent detection according to afirst embodiment. Coherent detection generally refers to transmitting asignal at a certain frequency f, and detecting the signal at that samefrequency f. Signals at other frequencies are considered noise. A mixer10 and an integrator 12 are together referred to as a correlator, whichperforms synchronous demodulation, or correlation, to reject noiseand/or interferers. In some embodiments, a mixer includes an operationalamplifier and a resistor pair including a variable resistor, where anoutput voltage of the mixer is a function of the input voltagemultiplied by the ratio of the two resistors. In some embodiments, anintegrator includes an operational amplifier, a feedback capacitorcoupled to the input and output of the operational amplifier, and aresistor coupled to the input of the operational amplifier, where anoutput voltage of the integrator is equal to the inverse of the resistorand capacitor product multiplied by the integration of the input voltageover a period of time. Alternatively, other conventional mixer andintegrator configurations can be used.

A signal generator 8 generates an excitation signal sin(ωt), whereω=2πf. The excitation signal sin(ωt) is multiplied by a referencevoltage Vref. The resulting signal Vref*sin(ωt) is modulated accordingto a measured capacitance of the capacitor Cm. This modulated signal isamplified by a low-noise amplifier 9, input to the mixer 10 and mixedwith the original excitation signal sin(ωt). The mixer 10 multiples thetwo input signals, the modulated and amplified excitation signal and theexcitation signal. The multiplied signals are then integrated over atime period T by the integrator 12. The time period T is a multiple ofthe period 1/f. Multiplying the two sine wave signals results in a DCvoltage term (Cm/2Cf)Vref plus a sine term at twice the frequency, whichwhen integrated over a multiple of the frequency cancels out, leavingonly the DC voltage term. This is the result when only an ideal signalis present. When noise is introduced, the noise is also multiplied bythe excitation signal sin(ωt) and integrated. The output voltage Voutcan be represented as follows:

$\begin{matrix}{V_{out} = {{\frac{C_{m}}{2C_{f}}V_{ref}} + {\int_{0}^{T}{{n(t)}{\sin \left( {2\pi \; f\; t} \right)}\ {t}}}}} & (1)\end{matrix}$

where T is a multiple of 1/f and the noise is represented as n(t). Theintegrator 12 provides a band-pass filtering function with a peak aroundf so that the noise, included in the second term in equation (1), isfiltered out. The output voltage Vout is the DC voltage term that can besubsequently sampled using an ADC. There is no dynamic signal to besampled.

FIG. 7 illustrates an exemplary frequency response of the circuit ofFIG. 6 for an excitation frequency f equal to 300 kHz. In an exemplaryapplication, the circuit of FIG. 6 is configured for narrow band passfiltering, and the corresponding narrow band frequency response of FIG.7 shows that the circuit is very selective about 300 kHz. Otherfrequencies are filtered out.

In addition to filtering out the noise, the coherent detection circuitshown in FIG. 6 can also be easily adapted to generate excitationsignals of alternate frequencies so as change the band-pass function.This tuning does not require changing the LNA, the mixer 10, or theintegrator 12. The signal generator 8 is simply changed to generate theexcitation signal at the alternate frequency. In contrast, the BPFcomponent in the conventional analog front end circuit in FIG. 5, e.g.the resistors and capacitors within the BPF, need to be adjusted tochange the band-pass function.

Although the above application is described above in terms of sinewaves, it is understood that other waveforms can be used to applycoherent detection. Equation (1) can be generalized to:

V ₀=∫₀ ^(T) E(t)C(t)dt+∫ ₀ ^(T) n(t)C(t)dt   (2)

where E(t) is an excitation signal supplied to the capacitor Cm and C(t)is a correlation signal input to the mixer. E(t) and C(t) can be anywaveform such that E(t) and C(t) are correlated. E(t) and C(t) arechosen such that the integration of E(t)C(t) is maximized and theintegration of n(t)C(t) is minimized. C(t) is selected for leastcorrelation to noise. The time period T is a multiple of the E(t)*C(t)period.

Implementation of the mixer 10 is a non-trivial task. The mixer 10 isconfigured to multiply two input analog signals, the modulated andamplified excitation signal and the excitation signal. In someapplications, this multiplication function is to be linear. To achieve alinear transfer function, the mixer 10 uses 10-12 bit linear multiplier.Such a mixer is difficult to build and is expensive.

FIG. 8 illustrates a schematic circuit diagram of an exemplary mixingcircuit according to an embodiment. The mixing circuit includes twoinput ports, an In port and an LO port. The In port receives themodulated signal output from the amplifier 9 (FIG. 6). The LO portreceives the original excitation signal sin(ωt). Plus and minus portsrepresent a differential signal, as is well known in the art. The Inport can be made linear, but the LO port is simply a switch thatprovides a square wave response. This provides limited rejection ofundesired signals at the harmonics of the desired frequency. Forexample, 3rd harmonic of a square wave is only 8 dB below thefundamental; therefore, interference at 3*f would only see 8 dBattenuation.

In an alternative configuration, the function of the mixer and theintegrator are combined and simplified so as to reduce the complexityassociated with performing linear multiplication. Using a simplifieddescription, a mixer can include an operational amplifier and a resistorpair including a variable resistor, where an output voltage of the mixeris a function of the input voltage multiplied by the ratio of the tworesistors. An integrator includes an operational amplifier, a feedbackcapacitor coupled to the input and output of the operational amplifier,and a resistor coupled to the input of the operational amplifier, wherean output voltage of the integrator is equal to the inverse of theresistor and capacitor product multiplied by the integration of theinput voltage over a period of time. Notice is taken of the quantity 1/Rin the aforementioned relationship between the input voltage and theoutput voltage of the integrator. Since a multiplying function is neededto mix the modulated excitation signal and the excitation signal, suchas the function performed by the mixer 10 in FIG. 6, if the quantity 1/Rcan be appropriately modulated, the resistive element can be used toperform the multiplying function. A programmable resistive element canbe used to perform this function. Instead of discrete mixing andintegrator circuits, the two functions are combined as a singleintegrated circuit that includes a single operational amplifier, acapacitor, and a programmable resistive element.

FIG. 9 illustrates a simplified schematic block diagram of an analogfront end circuit using coherent detection according to a secondembodiment. A programmable resistive element Rin, an amplifier 14, andan integrating feedback capacitor Ci form an integrated circuit havingthe combined functionality of a mixer and an integrator. Theprogrammable resistive element is represented in FIG. 9 as Rin with anarrow. In some embodiments, the programmable resistive element Rin isimplemented as a digital array of resistors, shown in the expanded areain FIG. 9 as an array of resistors R1-Rx. Each resistor R1-Rx in thearray is coupled to a corresponding on-off switch S1-Sx. One or more ofthe resistors R1-Rx in the array can be turned on such that the overallconductance of the programmable resistive element Rin imitates a desiredwaveform, such as a sine wave. In this manner, an appropriatecombination of resistors in the array of resistors R1-Rx can be turnedon to represent the multiplication of the modulated excitation signaland the excitation signal, thereby performing the multiplicationfunction previously performed by the mixer 10 in FIG. 6.

The switches S1-Sx are controlled by a digitized waveform, such as adigitized sine wave. The conductance G(t) of the programmable resistiveelement Rin is equal to 1/R(t), which is proportional to the sine wave,where R(t) is the overall resistance of all turned on resistors in thearray of resistors R1-Rx. The signal to be digitized is a correlationsignal, which is correlated to the excitation signal generated by thesignal generator 18. In an exemplary application, the sine wave sin(ωt)is digitized. The resulting digital word is used to control the digitalswitches S1-Sx. This results in a conductance of the programmableresistor Rin that has the characteristic of a sine wave, represented asa digitized sine wave sin(nT), shown in FIG. 7, where “nT” indicates thesine wave is quantized, both in value and in time. The digitized sinewave sin(nT) is a summation of the piece-wise components of theprogrammable resistor array over the integration time period T. The timeperiod T is a multiple of the period 1/f. The digitized sine wavesin(nT) can be stored in memory and subsequently retrieved forapplication to the digital switches S1-Sx.

The modulated excitation signal input to the programmable resistiveelement Rin is also shaped like a sine wave, and as such the result atthe output of the programmable resistive element Rin is a multipliedvalue, which is then integrated according to the operational amplifier14 and the integrating feedback capacitor Ci. The voltage Vout outputfrom the integration is provided as input to an ADC (not shown) andsubsequently processed. The ADC samples the voltage Vout every period oftime, for example every 10 microseconds. After the voltage Vout issampled, the integrating feedback capacitor Ci is discharged by closingthe switch 16. After discharge, the switch 16 is opened for the nextcycle defined by the integrating time period T.

The analog front end circuits of FIGS. 6 and 9 utilize coherentdetection within a capacitance measurement application. In an exemplaryapplication, the analog front end circuit uses coherent detection tomeasure capacitance of a touch screen display. The analog front endcircuit provides excellent noise and interference immunity, and alsoprovides a higher signal to noise ratio.

The analog front end circuit of FIG. 9 combines the functionality of aconventional mixer and integrator by using a programmable resistiveelement. This combined circuitry performs the multiplication functionusing a digitized waveform instead of an analog waveform. The digitizedwaveform is much easier to generate than the analog waveform.Additionally, the combined functionality is performed using a singleoperational amplifier, as opposed to using a discrete mixer having afirst operational amplifier and a discrete integrator having a secondoperational amplifier.

The analog front end circuits of FIGS. 6 and 9 provide a continuous timesignal path, there is no discrete sampling function performed wheresampling is performed and then the charge across the capacitor isdischarged. The signal continuously flows through the mixer and theintegrator of FIG. 6, or through the programmable resistive element andthe integrating capacitor of FIG. 9, and because of this there is noaliasing due to time instant sampling. Anti-aliasing is done within thecorrelator. There is no need for a separate anti-aliasing filter.

The analog front end circuit of FIG. 9 has good linearity because theresistors in the programmable resistive element Rin and the integratingfeedback capacitor Ci are very linear.

The analog front end circuits of FIGS. 6 and 9 use less power than theconventional analog front end circuits, such as the analog front endcircuits of FIGS. 4 and 5. An ADC coupled to the analog front endcircuits of FIGS. 6 and 9 does not require as much power as an ADC, suchas the ADC used in FIG. 4, that is sampling an active analog signal. TheADC coupled to the analog front end circuits of FIGS. 6 and 9 can beslower and less precise. Also, performing the multiplication functionusing the programmable resistive element, as in FIG. 9, uses less powerand has a smaller area than using a discrete mixing circuit, as in FIG.6.

The analog front end circuits are described above as being applied to atouch screen application. Alternative applications are alsocontemplated.

The integrated mixer and integrator is shown in FIG. 9 as including aprogrammable resistor array coupled to an amplifier and feedbackcapacitor. This concept can be generalized to use a time-varyingimpedance element that changes in response to an input control. Thetime-varying impedance element is coupled to the amplifier and feedbackcapacitor. FIG. 10 illustrates a schematic diagram of an integratedmixing and integrating circuit including a transconductor as thetime-varying impedance element according to an embodiment. Thetransconductor has a programmable transconductance gm that is controlledusing digital or analog control C. The transconductance gm can bechanged over time to achieve a multiplication operation.

FIG. 11 illustrates a schematic diagram of an integrated mixing andintegrating circuit including a voltage to current converter v2 i and acurrent digital to analog converter (IDAC) as the time-varying impedanceelement according to an embodiment. The voltage to current converter v2i converts an input voltage to a corresponding current, which issupplied to the IDAC. The IDAC has a programmable gain that iscontrolled using digital or analog control C. The effective impedancecan be changed over time to achieve a multiplication operation.

FIG. 12 illustrates a schematic diagram of an integrated mixing andintegrating circuit including a programmable capacitive element as thetime-varying impedance element according to an embodiment. Theprogrammable capacitive element functions similarly as the programmableresistive element of FIG. 9 except for the use of capacitors instead ofresistors. The capacitors in the programmable capacitive element areturned on or off to achieve a desired time-varying gain, which functionsas the multiplication operation in the integrated mixing and integrationcircuit.

The integrated mixing and integrating circuits shown in FIGS. 9-12 canbe used in applications alternative to touch screens including, but notlimited to, radio frequency and thermal applications.

The programmable resistive element Rin, the switch 16, the amplifier 14,and the integrating feedback capacitor Ci in FIG. 9 are collectivelyreferred to as a correlator. The integrating feedback capacitor Ci is afixed capacitor. The programmable resistive element Rin is time-varyingand represented as R(t). The relationship of the output voltage Vout tothe input voltage Vin is:

$\begin{matrix}{{Vout} = {\frac{1}{C}{\int_{0}^{T}{\frac{{Vin}(t)}{R(t)}\ {t}}}}} & (3)\end{matrix}$

where C represents the capacitance of the integrating feedback capacitorCi. Equation (3) can be rewritten as:

$\begin{matrix}{{Vout} = {\frac{1}{C}{\int_{0}^{T}{{G(t)}{{Vin}(t)}\ {t}}}}} & (4)\end{matrix}$

where G(t) is the conductance of the programmable resistive element,G(t)=1/R(t).

FIG. 13 illustrates an output voltage Vout versus time curve for thecorrelator of FIG. 9, under the simplified conditions where theresistance R(t) and the input voltage V(t) are constant. The result is alinear function due to integration of a constant value in equation (4).As the positive input of the amplifier 14 (FIG. 9) is referenced toground, the output voltage Vout is reset to 0V when the integratingfeedback capacitor Ci is discharged, which corresponds to a newintegration period starting at t=0. The longer the time period, thegreater the output voltage Vout. In implementation, the output voltageVout is limited to the system supply voltage Vdd supplied to theamplifier 14. As such, once the output voltage Vout reaches the supplyvoltage Vdd, the output voltage Vout no longer increases with time, butinstead remains constant at the supply voltage level. The ramificationis that if the application requires a larger time period t than the timefor the output voltage to reach the supply voltage Vdd, the correlatorof FIG. 9 is ineffective for the given value of the integrating feedbackcapacitor Ci. However, the slope of the output voltage Vout versus timecurve is inversely related to the capacitance Ci. If the capacitance Ciis increased, then the slope of the curve is reduced, which means ittakes a longer period of time for the output voltage to reach the supplyvoltage limit. Therefore, implementation of a larger capacitor enablesthe implementation of a longer time period for integration. However, alarger capacitor has a greater physical area. A larger capacitor alsoresults in reduced sensitivity, since over the same integrating timeperiod, a larger capacitor results in a lower integrated output voltagelevel than a smaller capacitor. In general, depending on the applicationand the corresponding integrating time period, the size of theintegrating feedback capacitor Ci is optimized to result in the largestpossible output voltage Vout. If the integration time period is shorter,then the size of the capacitor is smaller. If the integration timeperiod is longer, then the size of the capacitor is larger. Having afixed capacitance does not provide flexibility for varying applications.

In an exemplary touch screen display application, the frequency responseis relatively slow, for example hundreds of kHz, and therefore theintegration time period is relatively long and the RC product isrelatively large. A large RC results in large physical area and uses alarge amount of power to operate.

To address these limitations associated with a correlator having a fixedcapacitance, the correlator of FIG. 9 can be adapted to include a chargeadjustment circuit. The correlator and charge adjustment circuit arecollectively referred to as a mixed signal correlator. As describedabove, the correlator of FIG. 9 has both mixing and integratingfunctionality. In some embodiments, the correlator is configured as asimple integrator. As a simple integrator, a fixed impedance element,such as a resistor, can be used instead of a time-varying impedanceelement, such as the programmable resistive element. Although a mixedsignal correlator is subsequently described, it is understood that theconcepts can be applied to an integrator.

FIG. 14 illustrates a simplified schematic block diagram of a mixedsignal correlator according to an embodiment. The mixed signalcorrelator includes the correlator of FIG. 9, including the amplifier14, the integrating feedback capacitor Ci, and the programmableresistive element Rin. The positive input of the amplifier 14 in FIG. 14is coupled to a known voltage Vcm, such as one-half the supply voltageVdd. The mixed signal correlator also includes two comparators 19 and20, switches 22, 24, 26, 28, and 30, a charge dump capacitor Cd, and alogic/counter 32.

FIG. 15 illustrates an exemplary timing diagram corresponding tooperation of the mixed signal correlator of FIG. 14. The timing diagramshows the output voltage Vout versus time. The switches 22-30 are allshown to be open in FIG. 14, this is merely for illustration. During thecourse of operating the mixed signal correlator, various combinations ofthe switches are turned on an off, as will be described in connectionwith the timing diagram below.

After each integration period, the switch 16 is closed and theintegrating feedback capacitor Ci is discharged. The switch 16 is thenopened for the duration of the next integration period.

The timing diagram shows an integration period starting point at t=0.The output voltage Vout at the start of an integration period is equalto voltage Vcm supplied at the positive terminal of the amplifier 14,which in this case is one-half the supply voltage Vdd. The comparator 19compares the instantaneous output voltage Vout to a threshold highvoltage Vth, and the comparator 20 compares the instantaneous outputvoltage Vout to a threshold low voltage Vtl. As time increases from t=0,the output voltage Vout rises until it reaches the threshold highvoltage level Vth at time t1. When the output voltage Vout equals orexceeds the threshold high voltage Vth, the comparator 19 signals thelogic/counter 32 to perform a charge dump, or voltage adjustment,operation so that the output voltage Vout is reduced and remains withinthe supply voltage range. The threshold high voltage Vth is set to avalue less than the supply voltage Vdd, and the threshold low voltageVtl is set to a value greater than zero.

The logic/counter 32 controls the switches 22-30. While the outputvoltage Vout is within the threshold high and low voltage range, Vth andVtl respectively, the switches 26 and 30 are closed and the switches 22,24, and 28 are open so that the charge dump capacitor Cd is discharged.When the comparator 19 signals that the output voltage Vout equals orexceeds the threshold high voltage Vth, such as at time t1, the switches30 and 26 are opened, the switch 24 stays open, then switches 22 and 28are closed. The dump capacitor charges to reference voltage Vr and thecharge Vr*Cd is dumped to the negative terminal of the operationalamplifier 14, which causes a negative voltage adjustment −Vj in theoutput voltage Vout. The amount of voltage drop −Vj is determinedaccording to the reference voltage Vr and the capacitances of the chargedump capacitor Cd and the integrating feedback capacitor Ci.Specifically, voltage drop −Vj=Vr(Cd/Ci). In the exemplary applicationshown in the timing diagram of FIG. 15, the voltage adjustment Vj isequal to one-half the difference between the threshold high voltage Vthand the threshold low voltage Vtl, thereby dropping the output voltageVout to the midway point between the two threshold voltages. The timingdiagram shows application of the voltage adjustments, such as at timet1, as an instantaneous response when reaching the threshold voltage.This is merely for illustrative purposes. In practice, there is a delaycorresponding to charging the dump capacitor Cd.

After the output voltage adjustment at time t1, the switches 22 and 28are opened, the switch 24 remains open, and the switches 26 and 30 areclosed so that the charge dump capacitor Cd discharges. As timeincreases, t>t1, the output voltage Vout increases until it againreaches the threshold high voltage Vth at time t2 and the output voltagedownward adjustment, −Vj, is again triggered and initiated.

The secondary curve 3 in the timing diagram reflects the output voltageVout if the circuit were configured without the voltage adjustments, asin the correlator of FIG. 9, and the circuit were not limited by thesupply voltage Vdd. In practice, the output voltage Vout would not beable to exceed the supply voltage Vdd.

After the second output voltage adjustment at time t2, the switches 22and 28 are opened, the switch 24 remains open, and the switches 26 and30 are closed so that the charge dump capacitor Cd discharges. As timeincreases, t>t2, the output voltage Vout increases. However, in thiscase the output voltage Vout eventually begins to decrease in valuewithout reaching the triggering threshold high voltage Vth. The drop inoutput voltage Vout is due to a change in sign of the input voltage Vin,such as at time t3. As time increases, t>t3, the output voltage Voutcontinues to decrease until it reaches the threshold low voltage levelVtl at time t4. When the output voltage Vout equals or is less than thethreshold low voltage Vtl, the comparator 20 signals the logic/counter32 to perform a charge dump operation so that the output voltage Vout isincreased and remains within the supply voltage range.

When the comparator 20 signals that the output voltage Vout equals or isless than the threshold low voltage Vtl, the switches 26 and 30 areopened, the switch 22 remains open, then the switches 24 and 30 areclosed so as to appropriately charge the charge dump capacitor Cd. Thedump capacitor charges to reference voltage −Vr and the charge −Vr*Cd isdumped to the negative terminal of the operational amplifier 14, whichcauses a positive voltage adjustment +Vj in the output voltage Vout. Theamount of voltage gain +Vj is determined according to the referencevoltage Vr and the capacitances of the charge dump capacitor Cd and theintegrating feedback capacitor Ci. Specifically, voltage gain+Vj=Vr(Cd/Ci).

After the third output voltage adjustment at time t4, the switches 24and 28 are opened, the switch 22 remains open, and the switches 26 and30 are closed so that the charge dump capacitor Cd discharges. As timeincreases, t>t4, the output voltage Vout increases until it againreaches the threshold high voltage Vth at time t5 and the output voltagedownward adjustment, −Vj, is again triggered and initiated.

After the fourth output voltage adjustment at time t5, the switches 22and 28 are opened, the switch 24 remains open, and the switches 26 and30 are closed so that the charge dump capacitor Cd discharges. As timeincreases, t>t5, the output voltage Vout increases until the end of theintegration period at time T.

It is understood that the circuitry used to generate the output voltageadjustments +Vj and −Vj is but one example and that other circuitconfigurations can be used to achieve the same output voltageadjustments.

The logic/counter 32 maintains a running count Cn of the number ofoutput voltage adjustments made during an integration period. In thecase of a voltage adjustment drop, −Vj, when the output voltage Voutreaches the threshold high voltage Vth, the count increases by one, +1.In the case of a voltage adjustment gain, +Vj, when the output voltageVout reaches the threshold low voltage Vtl, the count decreases by one,−1. As applied to the timing diagram of FIG. 15, the count at time T isequal to +2 due to three voltage drops, +3, and one voltage gain, −1.

To determine the actual integrated output voltage over the integrationperiod T, the output voltage Vout at time T is added to the product ofthe current count Cn and the voltage adjustment Vj. As applied to thetiming diagram of FIG. 15, the actual integrated output voltage equalsthe current output voltage Vout+2Vj, since the count Cn corresponding tothe timing diagram of FIG. 15 is +2. The actual integrated outputvoltage over the integration period T is also referred to as thereconstructed output voltage.

FIG. 16 illustrates a circuit for implementing the mixed signalcorrelator of FIG. 9 according to an embodiment. An ADC 34 is coupled toreceive the output voltage Vout. The ADC 34 also inputs a referencevoltage Vr. A digital output of the ADC 34 is coupled to a summingcircuit 36. A multiplier 38 is coupled to the logic/counter 32 toreceive the count Cn, where the count Cn is the count at time T, the endof the integration period. The multiplier 38 also receives as input aconstant G, where G is a digital representation of the voltageadjustment Vj. The multiplier 38 outputs the product Cn*G to the summingcircuit 36, where the converted digital output voltage is added to theproduct Cn*G. The output Dr of the summing circuit 36 is the digitalrepresentation of the reconstructed output voltage. The output Dr is aweighted sum of an analog integrator output and a digital counteroutput.

Using the output voltage adjustment technique of the mixed signalcorrelator, the output voltage Vout is maintained within the rangebounded by the threshold high voltage Vth and the threshold low voltageVtl, and the actual integrated output voltage over the integrationperiod can be reconstructed as if the limit of the supply voltage didnot exist. Using the output voltage adjustment technique of the mixedsignal correlator also enables the use of a smaller capacitor forcapacitance measuring, which results in greater sensitivity. Thistechnique is also independent of the integration period, the integrationperiod can be set as long or as short as necessary. In this manner, theintegration time is decoupled from the size of the capacitor. Themaximum integration time can be increased by adding bits to the counter32. Additional counter bits also increases the final resolution of thefinal output.

In an alternative embodiment, the comparator functions performed by themixed signal correlator are performed in software. For example, thecomparators 19 and 20 can be replaced by software, operating for examplein the control/logic block 32, where the software compares theinstantaneous output voltage Vout to high and low threshold valuesstored in memory.

The relationship of the input voltage Vin to the output voltage Vout, aswell as the value of the constant G, is determined according to theratio of the two capacitors Cd/Ci. This ratio is very stable,essentially constant. However, some applications may require a moreaccurate value. Additionally, the actual capacitances may be differentthan their stated values. In other words, some applications may requiremeasured, more accurate determination of the constant G. Such adetermination can be achieved using a calibration process for the mixedsignal correlator.

FIG. 17 illustrates a simplified schematic block diagram of a mixedsignal correlator configured to perform a calibration process accordingto an embodiment. The mixed signal correlator shown in FIG. 17 is themixed signal correlator of FIG. 14 including the ADC 34 of FIG. 16 aswell as a switch 40. Normal operation of the mixed signal correlator,such as the operation described in relation to FIGS. 14-16, is performedby connecting the switch 40 to the input voltage Vin. To calibrate thesystem, two steps are performed. In a first step, the integratingfeedback capacitor Ci is discharged, and the input is then shorted toground by connecting the switch 40 to ground while the voltageadjustment circuit is disabled, such as by opening switch 28. The outputvoltage Vout is integrated over the integration period T, digitized bythe ADC 34, and output from the ADC 34 as digital output D0. Theintegrating feedback capacitor Ci is then discharged. In a second step,the input is again shorted to ground, and the logic/counter 32 forcesone voltage adjustment, even though neither comparator 19 or 20 signaledto do so. The forced voltage adjustment is achieved by appropriatelyswitching the switches 22-30 to generate either a voltage adjustmentdrop −Vj or a voltage adjustment step +Vj. The output voltage Vout isintegrated over the integration period T, digitized by the ADC 34, andoutput from the ADC 34 as digital output D1.

FIG. 18 illustrates a voltage output Vout versus time curve for thefirst step of the calibration process, where the digital output D0 isdetermined. The non-horizontal output voltage curve in FIG. 18 indicatesextraneous voltages, such as offset and leakage voltages, present at theoutput when the input voltage is shorted to ground. FIG. 19 illustratesa voltage output Vout versus time curve for the second step of thecalibration process, where the digital output D1 is determined. Duringthe second step of calibration, the voltage output Vout may exceed thethreshold voltage, as shown in FIG. 19. Exceeding the threshold voltageis acceptable in this case as long as the voltage output Vout does notreach the supply voltage Vdd. Subtracting the digital output D0 from thedigital output D1 results in the constant G, which is the digitalrepresentation of the adjustment voltage Vj. In this manner, the valueof constant G is an actual measured value, it is not an estimated valuebased on the stated specifications of the capacitors Cd and Ci.

The calibration process enables the circuit to determine the value ofthe constant G. The calibration process can be run one time orperiodically. Periodic calibration enables compensation for capacitancechanges over time, due to for example temperature effects or aging. Thecalibration process does not require additional hardware other than aswitch to short the input voltage. The mixed signal correlator itself isused to perform the calibration. The calibration process also enablesrelaxation of the Cd to Ci capacitor matching requirements needed toachieve a desired adjustment voltage value, and reduces if noteliminates the negative impact of mismatched capacitors.

The mixed signal correlator described above includes a single counterfor maintaining a running count of both positive and negative voltageadjustments. Alternatively, separate counters can be used, a firstcounter to count the positive voltage adjustments and a second counterto count the negative voltage adjustments. In this implementation, afirst calibration can be performed to determine a first constant G1corresponding to positive adjustment voltages +Vj, and a secondcalibration can be performed to determine a second constant G2corresponding to negative adjustment voltages −Vj. The actual integratedoutput voltage can be determined by subtracting the actual integratedoutput voltage corresponding to positive voltage adjustments, using thefirst constant G1, and the actual integrated output voltagecorresponding to the negative voltage adjustments, using the secondconstant G2.

The present application has been described in terms of specificembodiments incorporating details to facilitate the understanding of theprinciples of construction and operation of the mixed signal correlator.Many of the components shown and described in the various figures can beinterchanged to achieve the results necessary, and this descriptionshould be read to encompass such interchange as well. As such,references herein to specific embodiments and details thereof are notintended to limit the scope of the claims appended hereto. It will beapparent to those skilled in the art that modifications can be made tothe embodiments chosen for illustration without departing from thespirit and scope of the application.

1. An integration circuit comprising: a. an input control switchconfigured to switch to a first position coupled to an input voltagesignal and to a second position coupled to ground; b. an integratorcoupled to an output of the input control switch, wherein the integratoris configured to output an integrated output voltage; c. a voltageadjustment circuit coupled to the integrator, wherein the voltageadjustment circuit is configured to adjust the integrated output voltageby a voltage adjustment; and d. a logic circuit coupled to the voltageadjustment circuit and to the input control switch, wherein the logiccircuit is configured to control the voltage adjustment circuit and theinput control switch, further wherein when the input control switch isset to the first position the integrator integrates the input voltagesignal and the voltage adjustment circuit adjusts the integrated outputvoltage by the voltage adjustment if the integrated output voltagereaches one or more defined limits, and when the input control switch isset to the second position the integrator, the voltage adjustmentcircuit, and the logic circuit are configured to perform a calibrationprocess that measures a value of the adjustment value.
 2. Theintegration circuit of claim 1 wherein the integrator further comprises:a. a resistive element coupled to the output of the input controlswitch; b. an amplifier coupled to an output of the resistive element;and c. an integrating feedback capacitor coupled to an input of theamplifier and to an output of the amplifier.
 3. The integration circuitof claim 2 wherein the voltage adjustment circuit comprises a chargedump capacitor, further wherein the value of the voltage adjustment isset by a capacitance ratio of the charge dump capacitor and theintegrating feedback capacitor.
 4. The integration circuit of claim 3wherein the voltage adjustment circuit further comprises a plurality ofswitches, wherein the charge dump capacitor is coupled to theintegrating feedback capacitor via a first switch of the plurality ofswitches, and the plurality of switches are coupled to the logiccircuit.
 5. The integration circuit of claim 1 further comprising ananalog-to-digital convertor coupled to the output of the integrator toconvert the integrated output voltage to a digital value at eachintegration time period.
 6. The integration circuit of claim 5 whereinthe logic circuit is configured to perform the calibration process bymeasuring the digital value output from the analog-to-digital converterwhile the input control switch is in the second position, forcing thevoltage adjustment circuit to adjust the integrated output voltage bythe voltage adjustment while the input control switch is in the secondposition, and measuring the digital value output from theanalog-to-digital converter after the forced voltage adjustment whilethe switch is in the second position.
 7. The integration circuit ofclaim 1 wherein the voltage adjustment value is a fixed value Vj.
 8. Theintegration circuit of claim 1 further comprising a comparison circuitcoupled to the integrator, wherein the comparison circuit is configuredto receive the integrated output voltage, to compare the integratedoutput voltage to the one or more defined limits, and to output acomparison result to the logic circuit.
 9. The integration circuit ofclaim 1 wherein the logic circuit includes program instructionsconfigured to perform the steps of comparing the integrated outputvoltage to the one or more defined limits, and to control the voltageadjustment circuit according to a comparison result.
 10. The integrationcircuit of claim 1 wherein the resistive element has a fixed impedance.11. The integration circuit of claim 1 wherein the resistive element hasa time-varying impedance.
 12. A method of calibrating an integrationcircuit, the method comprising: a. coupling an input of an integrator toground; b. discharging an integrating feedback capacitor within theintegrator, wherein an output of the integrating feedback capacitoroutputs an integrated output voltage according to a current chargeaccumulated by the integrating feedback capacitor; c. measuring theintegrated output voltage to determine a first calibration voltage; d.applying a charge dump to the integrating feedback capacitor therebyadjusting the integrated output voltage; e. measuring the integratedoutput voltage after application of the charge dump to determine asecond calibration voltage; f. calculating a difference between thefirst calibration voltage and the second calibration voltage todetermine a measured adjustment voltage value that corresponds to thecharge dump; and g. discharging the integrating feedback capacitor. 13.The method of claim 12 wherein calculating the difference between thefirst calibration voltage and the second calibration voltage comprisesconverting the first calibration voltage to a first digital value,converting the second calibration voltage to a second digital value, andcalculating a difference between the first digital value and the seconddigital value.
 14. The method of claim 12 further comprising: a.coupling the input of the integrator to receive an input voltage signal;b. comparing the integrated output voltage to one or more thresholdvalues to determine if the integrated output voltage is within a voltagerange; c. adjusting the charge on the integrating feedback capacitor byapplying the charge dump if the integrated output voltage is not withinthe voltage range, thereby maintaining the integrated output voltagewithin a voltage range; d. determining an accumulated voltage changecorresponding to a number of adjustments in charge applied within anintegrating period multiplied by the measured adjustment voltage value;and e. determining a total integration voltage over the integratingperiod by adding the accumulated voltage change to the integrated outputvoltage at the end of the integrating period.
 15. The method of claim 14wherein adjusting the charge comprises decreasing the charge on thecapacitor if the integrated output voltage is greater than or equal to ahigh threshold value, and increasing the charge on the capacitor if theintegrated output voltage is less than or equal to a low thresholdvoltage, wherein decreasing the charge on the capacitor decreases theintegrated output voltage and increasing the charge on the capacitorincreases the integrated output voltage.
 16. The method of claim 14wherein comparing the integrated output voltage to one or more thresholdvalues is performed in software.
 17. The method of claim 14 whereincomparing the integrated output voltage to one or more threshold valuesis performed using one or more comparators.
 18. The method of claim 14wherein adjusting the charge on the capacitor results in adjusting theinstantaneous integrated output voltage.
 19. The method of claim 14wherein determining the total integration voltage comprises convertingthe integrated output voltage to a digital value at each integrationtime period and adding the accumulated voltage change to the digitalvalue.
 20. The method of claim 12 wherein the measured adjustmentvoltage value comprises a fixed value.